The present invention relates to semiconductor integrated circuits (ICs), and more particularly to a back-end-of-the-line (BEOL) interconnect that has a modified structure that enhances the reliability of the IC. The present invention is also related to a method for fabricating the semiconductor IC structure containing the modified interconnect structure.
Damascene processes are well known methods to form metal features such as lines or vias in semiconductor devices. In a typical damascene process a dielectric layer is deposited on a substrate and a portion of the dielectric is etched away in accordance with a mask pattern. The etched areas in the dielectric layer are lined with a barrier metal and then filled with a metal. Excess liner and metal deposited over the dielectric layer is removed in a planarization process.
The vias and lines may be formed in a separate damascene process known as single damascene. To form a layer of metal lines on a substrate, a dielectric layer is deposited and a portion of the dielectric layer is etched away in accordance to a mask pattern which corresponds to the desired line pattern. A metal liner is then deposited on the dielectric layer and in the etched line areas in the dielectric layer. The etched line areas are then filled with a metal and excess metal and liner on top of the dielectric layer is removed in a planarization process. A layer of vias, or vertical connections, are formed in a similar process with a mask pattern corresponding to the desired via pattern. In a single damascene process to form a layer of vias and lines requires two metal fill steps and two planarization steps.
The vias and lines may also be formed in a dual damascene process. A thicker dielectric layer is deposited on a substrate and the dielectric layer is etched according to a mask pattern which corresponds to both the desired via pattern and the desired line pattern. A liner is deposited on the dielectric layer and in the etched areas in the layer. The etched areas are filled with a metal and the excess metal and liner are removed by a planarization process.
FIGS. 1A-1D illustrate various prior art dual damascene structures. Each of the dual damascene structures shown comprises a first dielectric 100 that includes a metal interconnect or line 110 which extends perpendicular to the plane of the paper. A first patterned cap layer 120 is also present on a surface of the first dielectric 100. A second dielectric 130 is located atop the first dielectric 100. The second dielectric 130 has a dual damascene aperture, which includes a lower portion 148 and an upper portion 150, formed therein. The lower portion 148 is referred to in the art as a via, while the upper portion 150 is referred to in the art as a line.
The dielectrics used in each of the levels are typically comprised of silicon dioxide, a thermosetting polyarylene resin, an organosilicate glass such as a carbon-doped oxide (SiCOH), or any other type of hybrid related dielectric. The via 148 makes contact with the underlying interconnect 110, while the line 150 extends over a significant distance to make contact with other elements of the IC as required by the specific design layout. In the drawings, the portion of the cap layer 120 at the bottom of the via 148 has been removed, usually by a different etching chemistry than that used to etch the second dielectric 130. A patterned hard mask 122 is located atop the second dielectric 130.
It is conventional in the prior art to deposit a liner 140 over the entire interior of the structure before metallization. Liner 140 can be a single layer such as shown in FIG. 1A and FIG. 1C, or multiple layers 140, 145, as shown in FIGS. 1B and 1D. In FIGS. 1C and 1D, the liner 140 is not located on the bottom horizontal surface of the via 148. The liner 140, 145 is comprised of a refractory metal such as, for example, Ta, Ti, and W, or a refractory metal nitride such as TaN, TiN, and WN An optional adhesion layer, not specifically shown, can be used to enhance the bonding of the liner to the second dielectric layer 130.
A conductive material (not specifically shown) such as Al, W, Cu or alloys thereof is then deposited so as to completely fill the aperture providing conductively filled vias and conductively filled lines.
One major problem with the prior art interconnect structures shown in FIGS. 1A-1D is that it is difficult to obtain a good mechanical contact at normal chip operation temperatures. Additionally, the prior art interconnect structures oftentimes exhibit an open circuit or high resistance joint during reliability testing. Hence, there is a need for providing a new and improved interconnect structure that avoids the problems mentioned above. That is, an interconnect structure is needed that has and maintains good mechanical contact during normal chip operations and does not fail during various reliability tests such as thermal cycling and high temperature baking.
Problems with these prior art approaches has been the failure to make a good mechanical contact at a chip operation temperature. Failures also include an open circuit or a high resistance joint during reliability tests, i.e., thermal cycling, high temperature baking, etc. A major root cause of the failure is related to the thermal expansion coefficient mismatch between the conductive metal material and its surrounding dielectric material. The failure site is often observed at the via contact area.
Therefore, a need exists for a structure that enhances the reliability of the interconnection. An object of the present invention is to provide a novel interconnect structure to address the reliability concerns due to thermal expansion coefficient mismatch between the metal and dielectric.
Another object of the present invention is to provide novel interconnection structures with better technology extendibility for the semiconductor industry.
Another object of the present invention is to provide fabrication methods for creating the novel interconnect structures.